Tag Archive for OBERHEIM

Oberheim OB-Xa Program ROM Set


Click the link below to download the installation guide

This is a set of two replacement program ROMs for the Oberheim OB-Xa synthesizer, preprogrammed with the latest OB-Xa software revision (XA-GA0 and XA-G1) released in February 1982.

The new ROMs are based around modern CMOS EEPROM devices manufactured by Atmel Corporation (now a part of Microchip), adapted to a 24-pin DIP footprint with a custom PCB and gold plated pins. These devices are fully compatible with the original NMOS UV EPROMS (ST M2732A-2), have TTL and CMOS compatible inputs and outputs, and offer a significant reduction in current draw: up to a 68% decrease under normal operating conditions, and up to a 94% decrease in standby mode.

All ROM boards are hand assembled in the USA and tested in an Oberheim OB-Xa to guarantee their functionality.

If you are ordering these to repair an OB-Xa with a nonfunctional computer, please note that in our experience it is not uncommon for these units to have one or more dead logic ICs on the upper or lower control boards. Thus, it is possible that your original ROMs are fine, but another component in the system has failed.

ROM CRC-32 Checksums:
XA-GA0: F8268EA0

Technical notes about the waveform comparison screenshots:

This image compares how data line 0 changes when the CPU accesses the original XA-GA0 ROM versus the new XA-GA0 ROM. Two equivalent opcode fetches are shown in each screenshot. A CMOS Z80 CPU was used in this case, but the original NMOS Z80 will also work fine with these new ROMs.

From top to bottom, the waveforms shown are the chip select/output enable signals going to the ROM (active low and tied together in the OB-Xa; pins 18 and 20), data line 0 (pin 9), the M1 output from the Z80 CPU (pin 27), and the Z80 clock input (pin 6).

Per the Z80 user manual, the CPU initiates an opcode fetch (M1 cycle) with the falling edge of the M1 line (purple). One half clock cycle later (green), the CS/OE line (yellow) goes low, forcing the ROM to assert the data pointed to by the current address onto the data bus (blue; D0 is shown). Note how the original NMOS ROM has brief “glitches” in the data output when the CS/OE line changes while the new CMOS ROM does not; this is inconsequential to the operation of the CPU, as the data bus is sampled with the rising clock edge of state T3, by which time the data lines are at a well-defined logic level. The period of slow rise seen on the data line is also normal and inconsequential; this occurs whenever the data bus is in a high-impedance state and climbs to supply at a rate determined by the time constant of the pull-up resistors and bus capacitance.